1. Field of the Invention
The present invention relates generally to a BiCMOS driver circuit with an improved low output level which is closer to ground than prior art circuits, both at full speed and with a static resistive load.
More particularly, the subject invention pertains to an improved BiCMOS (bipolar/CMOS mixed type) driver circuit as described wherein the driver circuit incorporates therein a gated diode pull-down with a low voltage drop, and in which a bipolar output transistor remains on for output voltages down to approximately 0.3 volts.
2. Discussion of the Prior Art
A conventional BiCMOS NAND circuit produces a low output level by turning on a gated diode between the output and ground. The gated diode cannot sink static current at output voltages below 1 VBE (.about.0.85 V). In practice, however, the output overshoots this level on waveform falling edges. If the driver's load is purely capacitive, the static low level can range from 0.3 V to 0.7 V, depending upon factors such as load capacitance and leakage currents.
The main advantages of designing driver circuits in BiCMOS rather than CMOS are a smaller delay for large load capacitances and a lower sensitivity of the delay to capacitance and temperature. The main performance disadvantages derive from the partial swing outputs of the BiCMOS circuit, which cause increased delays in following CMOS or BiCMOS circuits, have reduced noise margins, and can cause significant static power dissipation in following stages. As CMOS supply voltages are scaled down, these problems become more serious as the voltage drop of the gated diode does not scale down, and so is proportionately larger at smaller supply voltages.
Several full swing BiCMOS circuits have been proposed in the prior art in which an extra node is driven by a small CMOS inverter at the output. After the output falls, the voltage at the extra node rises and turns on a small transistor, and the output is then discharged to ground. These full swing circuits achieve full swing only under static conditions while discharging into capacitive loads. The added MOS transistors are relatively weak and do not affect the delay or shape of the initial transition, so a full swing driver circuit operating at full speed has the same output waveform as a conventional BiCMOS driver. Even at relatively low frequencies, the smaller initial transition still results in reduced drive in following CMOS or BiCMOS stages. It should also be noted that reducing an NFET's V.sub.GS from 3.6 V to 3.3 V or 3.0 V reduces its maximum output current by about 13% or 25%, respectively.
In general, the prior art provides other BiCMOS driver circuits of different designs, but the present invention provides the best design for this type of circuit at the present state of development of this technology. Masuda et al. U.S. Pat. No. 4,890,017 entitled CMOS-BICMOS GATE CIRCUIT discloses a high-speed operation, low-power consumption gate circuit comprising a combination of complementary field-effect-transistors and bipolar transistors and a discharge for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
Ueno U.S. Pat. No. 4,845,386 entitled BI-MOS LOGIC CIRCUIT HAVING A TOTEM POLE TYPE OUTPUT BUFFER SECTION describes a totem pole type output buffer section comprising a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. These NPN bipolar transistors are selectively switch-controlled by a first MOS FET. Another NPN bipolar transistor is darlington-connected to the pull-down NPN bipolar transistor, and is switch-controlled by the second MOS FET. The second MOS FET is of the same conductivity type as and has a gate connected to a gate of the first MOS FET.
Masuoka et al. U.S. Pat. No. 4,779,014 entitled BICMOS LOGIC CIRCUIT WITH ADDITIONAL DRIVE TO THE PULL-DOWN BIPOLAR OUTPUT TRANSISTOR describes a logic circuit which comprises at least one signal input terminal, an output terminal, an output circuit including a first bipolar transistor coupled between the output terminal and a reference potential terminal, to discharge the output terminal, and an MOS type logic circuit for supplying to the base of the first bipolar transistor a signal of a level corresponding to an input signal supplied to the at least one signal input terminal. The logic circuit further comprises a control MOS transistor coupled between a power source terminal and the base of the bipolar transistor, for supplying part of the base current to the bipolar transistor in response to a signal at the output terminal. In this patent, an implementation of a BiCMOS NAND driver using a low-drop gated diode is referred to as prior art, with the statement that the pull-down NPN transistor saturates. In fact, proper choice of the A/B width ratio allows the low output voltage to be set reliably below 0.5 V without driving QNPN2 into hard saturation.
Uragami et al. U.S. Pat. No. 4,694,203 entitled HIGH SPEED B-CMOS SWITCHING CIRCUIT describes a bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET for driving these transistors in a complementary manner, and a resistance load for discharging the electric charge stored in the base of one transistor. The threshold voltage of an NMOSFET constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the driver NMOSFET in the absence of the substrate effect, and the channel conductance of the driver NMOS-FET is so set that the threshold voltage of the CMOS inverter and the practical threshold voltage of the driver NMOSFET will be nearly the same.
Uragami et al. U.S. Pat. No. 4,678,943 entitled INVERTING LOGIC BUFFER BICMOS SWITCHING CIRCUIT USING AN ENABLING SWITCH FOR THREE-STATE OPERATION WITH REDUCED DISSIPATION discloses a switching circuit comprising a prestage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal can be obtained from an output terminal of the output stage. The prestage circuit includes a p-channel MOSFET and an n-channel MOSFET that receive input signals at their gates. The output stage includes two NPN transistors and that are connected in series. The drain output of the p-channel MOSFET is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET is applied to the base of the other of the transistors of the output stage. A third MOSFET is coupled between a power supply and the p-channel MOSFET and the n-channel MOSFET. When the third MOSFET is rendered nonconductive by a control signal, both other MOSFETs and both NPN transistors become nonconductive irrespective of the signal of the input terminal. Under this condition, the output terminal is in a floating state. Thus the switching circuit is a tri-state circuit.